The core of the real-time digital signal processing technology and logos are the digital signal processor. Digital signal processing is different from the ordinary scientific computing and analysis, it emphasizes the real-time computing, DSP In addition to the ordinary microprocessor emphasized the high-speed computing, control functions, but also for real-time digital signal processing, the processor structure, command systems, the command sequence to do a lot of change function of its structural features are as follows. (1) in a Harvard architecture Von Neumann structure of DSP chips commonly used data bus and program bus separation Harvard architecture Harvard architecture processor or improved faster instruction execution speed. Structure of the ① von Neumann (von Neuman) The structure of the best storage space, the program instructions and data share a storage space, use a single address and data Bus, fetch and fetch operands via a bus time-sharing carried out. During high-speed computing, not only can not be Fetch and fetch operands, while the month will result in a data transmission channel of the bottle shall "phenomenon, the skin of its work speed is slower. The ② Harvard (Harvard) structure The structure of the dual memory space, program memory and data memory dl alone defined the program bus and data bus can be independently addressed and independent access to programs and data to conduct an independent transmission, so that the operation of instruction fetch, instruction perform operations data to swallow leaves done in parallel, greatly increased the speed of data processing capabilities and the implementation of the Directive, and is very suitable for real-time digital signal processing. The ③ modified Harvard architecture Modified Harvard architecture is the use of double storage space and a number of bus, a program bus and data bus. Its characteristics are: a. to allow each other to transmit data in the program between the middle and data space, so that these data can be internal arithmetic instructions direct calls to enhance the flexibility of the chip. b. store instruction caches (Cache) and the corresponding instructions, repeat these instructions, just read into the first can be used continuously for, do not need to read again from the program memory, thereby reducing the instruction execution the time required. (2) multi-bus architecture Multi-bus architecture to ensure that the many visits to the program space and data space in a machine cycle. The TMS320C54x internal group program bus PB data bus CB, DB and RB, and the corresponding four address Bus PAD, CAB, DAB, and the RAB. Can take an instruction from the program memory in a machine cycle, from data Memory read two operands and write an operand to the data memory, greatly improving the speed of the DSP. Therefore, the DSP, the internal bus is a very important resources, the bus is more, the more complex functions can be completed. (3) pipeline structure DSP implementation of an instruction, through the fetch, decode, fetch operands and execution in several stages. In DSP, pipeline structure, and these stages overlap in the program is running. Operating the pipeline, such as 4, in the implementation of this section directive to in order to complete the plant behind the three instruction-fetch operands, decoding and fetch each instruction in order to reduce the conditions does not increase the clock frequency execution time of the instruction cycle is reduced to a minimum. (4) a dedicated hardware multiplier In the general-purpose microprocessor, the multiplication is done by software, ie, by additions and shifts, require more than one instruction cycle to complete. In the number of Ning signal processing using multiplication and addition operations, the DSP chip dedicated hardware multiplier, multiply-accumulate operation can be completed all cycles. (5) special D5P instruction In order to better meet the needs of the digital signal processing applications, the DSP instruction set of towels, designed some special DSP instructions. For example, on TMS320C54X in the MACD (multiply, accumulate and data move) instruction to perform the function of LT, DMOV, MPY and APAC are instructions. (6) short instruction cycle Earlier DSP instruction cycle is about 400 ns. With the development of integrated circuit technology, DSP widely used in sub-micron CMOS manufacturing Ding Yi, running faster and faster. TMS320VC5462 example. Its speed of operation up to 100 MIPS (million instructions per second). Fast instruction cycle makes the DSP; tablet in real time to achieve many digital signal processing applications.
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